- Lieu : Grenoble INP (GI Amphi C), 46 Avenue Félix Viallet, Grenoble
- Date : 28 novembre 2024
- Capacité d’accueil : 60 personnes
Contexte
Le laboratoire TIMA organise une journée thématique sur l’architecture et la microarchitecture des systèmes généralistes ainsi que le jeu d’instruction RISC-V comme substrat de choix pour la communauté. L’objectif est de réunir la communauté nationale et de permettre des discussions informelles autour de ces thématiques, qui prennent de l’importance dans le cadre du développement de systèmes souverains tels que définis par le Chips Act européen.
Programme préliminaire
- 9h – 9h30 : Café accueil
- 9h30 – 9h40 : Introduction de la journée
- 9h40 – 10h45 : Arch/uarch pour la performance 1/2
- Keynote : André Sintzoff (Thalès DIS)
- « Architecting Value Prediction around In-order Execution », Pierre Ravenel (Kalray/TIMA)
- 10h45 – 11h15 : Café
- 11h15 – 12h05 : Arch/uarch pour la performance 2/2
- « Address/Data Instruction Steering in Clustered General Purpose Processors », Chandana Deshpande (TIMA)
- TBA
- 12h05 – 13h30 : Repas
- 13h30 – 15h : Arch/uarch pour la sécurité
- Keynote : « Selective Speculation : Using Speculative Barriers for Spectre Mitigation », Ronan Lashermes (Inria/SED&LHS)
- TBA
- TBA
- 15h – 15h30 : Café
- 15h30 – 16h45 : Pot pourri (interaction HW/SW, modélisation & methodologie)
- TBA
- TBA
- TBA
- 16h45 – 17h : Outroduction de la journée
Programme détaillé :
Session 1 – Arch/uarch pour la performance I
Titre : TBA, André Sintzoff (Thalès DIS)
Abstract : TBA
Titre : « Value Prediction and In-order Execution », Pierre Ravenel (Kalray/TIMA)
Abstract : « In this work, we study how both value prediction based on address prediction and direct value prediction can be built into an in-order pipeline to unlock significant performance. We further show that the in-order execution property provides advantages in that the pipeline may speculate aggressively without suffering from any recovery penalty. Finally, we combine this data speculation infrastructure with a reworked cache hierarchy that relies on a fast first level cache that can be written speculatively. We show that such an in-order pipeline can reach a performance level that is comparable to an equally — although moderately — wide out-of-order processor, without requiring support for partial out-of-order execution such as out-of-order memory hazard handling or full-fledged register renaming. »
TBA
Session 2 – Arch/uarch pour la performance II
Titre : « Address/Data Instruction Steering in Clustered General Purpose Processors », Chandana Deshpande (TIMA)
Abstract : Although they differentiate between integer and floating-point datum, modern Instruction Set Architectures and their implementations do not differentiate integer datum used to address memory from integer datum used in purely arithmetic and logical computations. This is a perfectly reasonable choice as addresses are, in fact, integral quantities. This work aims to leverage this dichotomy to revisit hardware clustering, a well known microarchitectural technique used to mitigate the cost of scaling processor backend structures by dividing the backend into several mostly independent execution clusters. We show that by treating instructions as manipulating addresses or data and steering them to a « data » or an « address » cluster accordingly, reasonable cluster load balancing can be achieved without the need for complex steering policies.
TBA
Session 3 – Arch/uarch pour la sécurité
Titre : « Selective Speculation : Using Speculative Barriers for Spectre Mitigation », Ronan Lashermes (Inria/SED&LHS)
Abstract : Six years on, Spectre attacks continue to pose significant challenges to modern out-of-order processors. In this talk, we will present our latest findings on mitigating these vulnerabilities, as part of our contribution to the Arsene project from the PEPR Cybersécurité program. We propose new speculation barrier semantics, usage policies, and hardware implementations and evaluate the effectiveness of these mitigations, both in terms of performance impact and security enhancement.
TBA
TBA
Session 4 – Pot-pourri
TBA
TBA
TBA
Participation
La participation est gratuite dans la limite des places disponibles, mais obligatoire.
Le formulaire d’inscription est à l’adresse suivante : https://evento.renater.fr/survey/journee-thematique-soc-kbyrm59x
Contact
Arthur Perais (arthur.perais@univ-grenoble-alpes.fr)